Electronic systems use solid-state memory devices to store data, such as application programs, operating systems and real-time input and output information. The electronic systems, such as computers, computer system components and digital processing systems are built within space and budget constraints. The electronic systems often use more storage capacity as they become more complex. To meet the ever increasing demand for storage capacity and to stay within system space and budget constraints, memory device suppliers endeavor to increase memory cell density in the memory devices.
One type of solid-state memory device known in the art includes magnetic memory cells. These devices, known as magnetic random access memory (MRAM) devices are non-volatile, reprogrammable devices that include an array of magnetic memory cells. The magnetic memory cells may be of different types. For example, the memory cells can be magnetic tunnel junction (MTJ) memory cells or giant magneto-resistive (GMR) memory cells.
Generally, a magnetic memory cell includes a layer of magnetic film in which the orientation of magnetization is alterable and a layer of magnetic film in which the orientation of magnetization may be fixed or “pinned” in a particular direction. The magnetic film having alterable magnetization is referred to as a sense layer or data storage layer, and the magnetic film that is fixed is referred to as a reference layer or pinned layer. In an MTJ memory cell, an insulating barrier layer separates the sense layer and the reference layer.
Conductive traces referred to as word lines and bit lines are routed across the array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. A bit of information is stored in a memory cell as an orientation of magnetization in the sense layer at the intersection of a word line and a bit line. The orientation of magnetization in the sense layer aligns along an axis of the sense layer referred to as its easy axis. Magnetic fields are applied to flip the orientation of magnetization in the sense layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer.
The resistance through a memory cell differs according to the parallel or anti-parallel orientation of magnetization of the sense layer relative to the reference layer. The resistance is highest when the orientation is anti-parallel, which can be referred to as a logic “1” state, and lowest when the orientation is parallel, which can be referred to as a logic “0” state. The resistive state of the memory cell can be determined by sensing the resistance through the memory cell.
Magnetic memory cells are formed using pattern masks to fabricate the magnetic memory cell layers. Forming a high-density magnetic memory cell array can be very difficult in sub-micron magnetic memory devices. Alignment of the pattern masks is critical for achieving small memory cell sizes. The magnetic memory suppliers strive to improve fabrication and alignment techniques to form smaller magnetic memory cells and more densely packed magnetic memory cell arrays. In addition, magnetic memory suppliers make every effort to reduce fabrication complexity while forming smaller magnetic memory cells and less expensive magnetic memory cell arrays.